Thermal-Aware Floorplanning with Min-cut Die Partition for 3D ICs
نویسندگان
چکیده
منابع مشابه
Thermal-aware 3D Microarchitectural Floorplanning
Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck t...
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ژورنال
عنوان ژورنال: ETRI Journal
سال: 2014
ISSN: 1225-6463
DOI: 10.4218/etrij.14.0113.1204